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HIP9022
PRELIMINARY
Data Sheet
October 1998
File Number 4509.1
Dual High Speed Laser Driver
The HIP9022 Dual High Speed Laser Driver is designed to operate with a constant current drain from the power supply. This current defines the laser operating power. The current is accurately controlled in the range of 0.5A to 2A to deliver constant optical power from the laser when used with an external Power FET and Power Sense resistor. The operating circuit allows flexibility in choosing driver current levels. Eight S/H circuits are multiplex bus controlled to provide analog data for the dual laser drivers. The bus is updated during the blanking period of the laser printer scan with a data rate up to 2.5MHz. A "thermo-electric-cooler" control circuit provides temperature control of the laser. Two on-chip ESD diodes protect each laser. A principle advantage of the Dual High Speed Laser Driver is accomplished by managing the high currents externally with discrete Power FETs and thereby not forcing large switching currents to exist on the same IC substrate with the precision control circuitry.
Features
* Dual High Speed Laser Driver with Data Rates up to 2.5MHz * 0.5A to 2A Range of Constant Current Source Controlled to 0.1% Full Scale * Low Signal Transients with Controlled Constant Current Switching * Laser Optical Power Controlled to Better than 0.5% * Thermoelectric Cooler (TEC) Circuit to Control Temperature to within 0.25oC * Multiplexed Sample/Hold (S/H) Bus Interface * Serial Diagnostic Bus with Multiplexed Output * High Current ESD Diodes for Laser Diode Protection
Applications
* Dual Laser Printer Driver
Ordering Information
PART NUMBER HIP9022AM TEMP. RANGE (oC) 0 to 100 PACKAGE 68 Ld PLCC PKG. NO. N68.95
Pinout
HIP9022 (PLCC) TOP VIEW
NC VDD ESD LASER PS-1 ESD LASER PS-1 ESD SHUNT DRAIN-1 ESD SHUNT DRAIN-1 ESD SHUNT DRAIN-1 ESD LASER GND ESD LASER GND ESD SHUNT DRAIN-2 ESD SHUNT DRAIN-2 ESD SHUNT DRAIN-2 ESD LASER PS-2 ESD LASER PS-2 RLY_IN RLY_OUT V9P 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 VUP1 SG_1 VLOW1 VEE GNDA1 GNDD1 CC1 XTEN1+ XTEN1CTC1-10K CTC1-27K LASERON1B OC1 TECFB1 TECREF1 TECGDR1 TRES1 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 OT1 NC INVERT RESETB DIAGINB NULLB SB_H NC VIN VCC A3 A2 A1 A0 DIAG NC TECREFR 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 VUP2 SG_2 VLOW2 GNDA2 GNDD2 CC2 XTEN2+ XTEN2CTC2-10K CTC2-27K LASERON2B OC2 TECFB2 TECREF2 TECGDR2 TRES2 OT2
4-1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. http://www.intersil.com or 407-727-9207 | Copyright (c) Intersil Corporation 1999
HIP9022
ESD LASERPS-1 6 7 ESD SHUNT DRAIN-1 4 5 3 ESD LASER GND GND 2 1 X ESD SHUNT ESD DRAIN-2 LASERPS-2 65 64 68 67 66 LASER P.S. 3 TO 5V A6 PD +12V 8 1F VDD NC 9 + VDD 62 ESDD1 9V REG. V/I REF. V9P A4 61 LD1 LD2 ESDD2 63 RLY_IN RLY_OUT V9P 1F VCC RELAY1
+9V LASER
VUP1 10 SG_1 11 VLOW1 12 -5V 1F 13 VEE GNDA1 14 GNDD1 15 CC1 16 XTEN1+ 17 12k XTEN1- 18 LASER GATE DRIVE
60
VUP2 SG_2
1F Q3
59 A3 +
58
A5
-
1F 57 GNDA2
11k OTA GATE 11k DRIVE AMP. VCC + - A2 CURRENT MONITOR 1k AMP. + A1 X10 56
RF3V49092
VLOW2
X IDL
GNDD2 CC2
55
0.1F
Q2 THERMAL RELATED COMPONENTS RS 0.25
54
XTEN2+
-
53 52
XTEN2-
THERM. COMP ON/OFF
CTC2-10K
0.02F 0.1F
51
CTC2-27K
CTC2-10K 19 50 CTC1-27K 20 30k O. C. COMP. + PU LASER_ON2B 49 OC2 48 TECFB2 47 TECREF2 46 TECGDR2 TRES2
-
21 LASER_ON1B OC1 22 PU
TECFB1 23
TEC DRIVER (THERMO ELECTRIC COOLER CIRCUIT) AND
TEC P.S. 3V
TECREF1 24 TECGDR1 25 OVER/UNDER TEMPERATURE COMPARATOR 45
Q1 RFD3055 OR EQUIV. TEC
44 TRES1 26 1.9V OT1 27 NC 28 SAMPLE/HOLD SYSTEM PD 29 INVERT PD 30 RESETB PU PU 31 DIAGINB PU 32 NULLB SB_H 33 34 NC 35 36 37 A3 +5V PU 38 A2 PU 39 A1 VTEST OUT
OT2 (THERMO-RESISTOR SENSES LASER TEMP., NEG. TEMP. COEF., TEC COOLS LASER.)
LASER DRIVER-1
LASER DRIVER-2
PU 40
PU 41 42 43 NC
NOTE: PU = 60k PULLUP RESISTOR TO VCC PD = 60k PULLDOWN RESISTOR TO GND = SCHMITT TRIGGER HYSTERESIS TECREFR (TEMP. REF. RESISTOR) 5 - 10k
VIN VCC
A0 DIAG
FIGURE 1. HIGH SPEED LASER DRIVER FUNCTIONAL BLOCK DIAGRAM SHOWN IN QUIESCENT P.S. CURRENT TEST MODE
-
+
4-2
HIP9022 Pin Descriptions
PIN NUMBER 1, 2 3, 4, 5 6, 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 SYMBOL ESD LASER GND Laser supply and system ground. DESCRIPTION
ESD SHUNT DRAIN-1 Laser diode ESD protection. SD LASER PS-1 VDD NC VUP1 SG_1 VLOW1 VEE GNDA1 GNDD1 CC1 XTEN1+ XTEN1CTC1-10K CTC1-27K LASERON1B OC1 TECFB1 TECREF1 TECGDR1 TRES1 OT1 NC INVERT Laser power supply ESD protection. Input for 12V power supply. No connection. Filter capacitor for internally generated shunt gate upper voltage level (1F). Drive output to shunt Power FET gate. Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1F). Input for -5V power supply. Analog Ground. Digital Ground. Gate drive to the current source Power FET. Times 10 constant current monitor amplifier input from the high side of the sense resistor. Times 10 constant current monitor amplifier input from the low side of the sense resistor. Thermal compensation short time constant where TTC = External C x 10k. (External C typically equal 0.02F). Thermal compensation long time constant where TTC = External C x 27k. (External C typically equal 0.1F). Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power FET OFF and the Laser ON. These pins have an internal pull-up. Laser over-current indicator flag. Feedback to stabilize the TEC loop. Feedback to stabilize the TEC loop. Thermo-Electric Cooler Power FET gate drive. Thermo-Resistor output to ground connection for TEC control. Laser out of temperature range indication. No connection. High input converts to operation with Pmos Current source and NDmos shunt Power FET external transistors. Low input converts to operation with NDmos Current source and Pmos high side shunt Power FET external transistors. This pin has an internal pull-down. When RESETB is held low, three reset actions occur. The LASERONB input is defeated to a Laser Off condition. The SG_1, 2 outputs are switched to VLOW when in the INVERT low mode and to VUP when in the INVERT high mode. The TEC amplifier is turned off to switch the TECGDR1, 2 outputs to Ground. This pin has an internal pull-down. Low level activates the diagnostic mode. This pin has an internal pull-up. Auto-zeros the S/H amplifier selected by address when held low. This pin has an internal pull-up. Samples the selected address when held low. The setup time for address is <25ns. This pin has an internal pull-up. No connection. Analog voltage sampled by selected S/H. The input voltage range is 0 to 5V. There is an internal voltage clamp for voltage outside of this range. There is an internal 2 - 3s filter for noise rejection. Input for 5V power supply. Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up.
30
RESETB
31 32 33 34 35 36 37
DIAGINB NULLB SB_H NC VIN VCC A3
4-3
HIP9022 Pin Descriptions
PIN NUMBER 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64, 65 66, 67, 68 (Continued) DESCRIPTION Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. Refer to the Table 1 Address Map. The A3 - A0 pins have an internal pull-up. Diagnostic output, A 0V - 5V analog signal output limits internally to a range of -0.3V to 5.3V. The output is the channel addressed by A0 - A3. No connection. External resistor to ground with a resistor value equal to the value of the thermo-resistor at the desired laser temperature. (Typically in the 5k to 10k range) Laser out of temperature range indication. Thermo-Resistor output to ground connection for TEC control. Thermo-Electric Cooler Power FET gate drive. Feedback to stabilize the TEC loop. Feedback to stabilize the TEC loop. Laser over-current indicator flag. Input control turns shunt Power FET gate drive ON/OFF with 5V CMOS logic. Low turns the shunt Power FET OFF and the Laser ON. These pins have an internal pull-up. Thermal compensation long time constant where TTC = External C x 27k. (External C typically equal 0.1F). Thermal compensation short time constant where TTC = External C x 10k. (External C typically equal 0.02F). Times 10 constant current monitor amplifier input from the low side of the sense resistor. Times 10 constant current monitor amplifier input from the high side of the sense resistor. Gate drive to the current source Power FET. Digital Ground. Analog Ground. Filter capacitor for internally generated shunt Power FET gate lower drive voltage level (1F). Drive output to shunt Power FET gate. Filter capacitor for internally generated shunt gate upper voltage level (1F). Filter capacitor bypass for internally generated 9V power source (1F). Relay output drive from an N-channel FET controls an external relay to switch the Laser power supply or power supply interlock ON/OFF for both Laser Drivers. Relay input control with 5V CMOS logic. A high switches on the relay. This pin has an internal pulldown. Laser power supply ESD protection.
SYMBOL A2 A1 A0 DIAG NC TECREFER OT2 TRES2 TECGDR2 TECREF2 TECFB2 OC2 LASERON2B CTC2-27K CTC2-10K XTEN2XTEN2+ CC2 GNDD2 GNDA2 VLOW2 SG_2 VUP2 V9P RLY_OUT RLY_IN ESD LASER PS-2
ESD SHUNT DRAIN-2 Laser diode ESD protection.
4-4
HIP9022
Absolute Maximum Ratings
Maximum Analog Supply Voltage, VDD . . . . . . . . . . . -0.3V to 14V Logic Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . -0.3V to 6V Analog Negative Supply Voltage, VEE . . . . . . . . . . . . . 0.3V to -5.5 Maximum Laser Protection Diode Current . . . . . . . . . . 10A, 200ns
Thermal Information
Thermal Resistance (Typical, Note 1) JC (oC/W) PLCC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Maximum Operating Junction Temperature, TJ . . . . . . . . . . . 100oC Maximum Storage Temperature Range, TSTG . . . . -55oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
Operating Conditions
VDD Supply Voltage Range, VDD . . . . . . . . . . . . . . 11.4V to 12.6V VCC Supply Voltage Range, VCC . . . . . . . . . . . . . . . . 4.5V to 5.5V VEE Supply Voltage Range, VEE . . . . . . . . . . . . . . . . -4.5V to -5.5V Laser Power Supply Range, VLAS . . . . . . . . . . . . . . . . . . 3V to 5V TEC Power Supply Range, VTEC . . . . . . . . . . . . . . . . . . . 3V to 5V Laser Operating Current Range, IDL . . . . . . . . . . . . . . . . . 0A to 2A TEC Operating Current Range, ITEC . . . . . . . . . . . . . . . . . 0A to 2A
Die Characteristics
Back Side Potential . . . . . . . . . . . . . . . . . . . . . . . . . -VEE , Substrate
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications
TJ = 100C, VDD = 12V, VCC = 5V, VEE = -5V, INVERT Low (Figure 1 Configuration) Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PARAMETER POWER SUPPLIES V9P Voltage, No External Load V9P Thermal Shutdown V9P Thermal Shutdown Recovery V9P Current Limiting VDD Power Supply Current VCC Power Supply Current VEE Power Supply Current
V9P
1F Tantalum Capacitor to V9P
150 65
9 25 1.5 -23
125 75 25 -
V
oC oC
mA mA mA mA
IDD ICC IEE
-75
LOGIC/DIGITAL INPUTS (A0-A3, NULLB and SB_H, LASERON1B, LASERON2B with 60k Pullup Resistors; INVERT, RESETB, RLY_IN 60k with Pulldown Resistors) Low Level Input Voltage High Level Input Voltage Minimum Hysteresis Low Level Input Current (Inputs with Pullups) High Level Input Current (Inputs with Pulldowns) CONSTANT CURRENT CONTROLLER OTA Gate Drive Amp. (A2) Voltage Output Range Current Monitor Amp. (A1) Gain Current Monitor Amp. Differential Sense Input Range Current Monitor Amp. Input Offset Current Monitor Amp. Common Mode Input Range SHUNT CURRENT SWITCH CONTROLLER Shunt Gate Output Rise/Fall time Propagation Delay, LASERONB1, 2 to SG_1, 2 VG AVS VIN VIO VIC -4 9.8 0 -5 0 10 VCC 10.2 500 5 5 V mV mV V VIL VIH VHYS IIL IIH 0 3.5 0.3 -140 1.5 VCC + 0.3 140 V V V A A
(Note 2) VUPPER = 2V, VLOWER = -1V, Gate Load = 5000pF, VUP1, 2; 1F Filter Capacitor to GND, VLOW1, 2; 1F Filter Capacitor to GND, Unless Otherwise Specified tR /tF tD 10% -90% Rise, 90% -10% Fall TJ = 100oC TJ = -25o C 0 -4 80 60 20 110 95 VCC VCC ns ns ns V V
Drive Output Voltage
VUPPER VLOWER
4-5
HIP9022
Electrical Specifications
TJ = 100C, VDD = 12V, VCC = 5V, VEE = -5V, INVERT Low (Figure 1 Configuration) Unless Otherwise Specified (Continued) SYMBOL IDRSW fSC TEST CONDITIONS MIN -1 0 TYP MAX 1 2.5 UNITS A MHz
PARAMETER Driver Maximum Output Current Shunt Controller Switching Frequency ANALOG SAMPLE/HOLD AMPLIFIERS Low Level Input Voltage Low Level Input Current High Level Input Voltage Minimum Hysteresis Analog Input Voltage Range Minimum Sample/Hold Pulse Width Droop Rate, Constant Current Addresses #'s 1, 2 Droop Rate, Other Addresses #'s 3 - 8 Maximum Analog Multiplexing Frequency DIAGNOSTIC OUTPUT (DIAG Output)
VIL IIL VIH VHYS VIN
0 -140 3.5 0.3 0 -
10 -
1.5 VCC + 0.3 VCC - 0.2 0.006 0.06 30
V A V V V s V/s V/s kHz
Voltage Follower Voltage Range Voltage Follower Maximum Clamp Voltage
VO VCL
0 -
-
VCC - 0.2 VCC + 0.3
V V
O. C. (OVER CURRENT) COMPARATOR (OC1, 2 Outputs) Threshold (%) O.C. Detection Output Voltage, Low Level Output Current, Low Level Output Voltage, High Level Output Current, High Level TEC REF. RESISTOR AND DRIVE OUTPUT TECREFR Output Voltage to Reference Resistor TECGDR1, 2 Drive Output Voltage OVER/UNDER TEMPERATURE COMPARATOR Under Temp. Limit Over Temp. Limit Output Voltage, Low Level Output Current, Low Level Output Voltage, High Level Output Current, High Level RELAY DRIVER Driver Output Current Drain to Source Resistance LASER PROTECTION DIODES See Figure 1 Maximum Diode Forward Voltage Drop Maximum Reverse Diode Current NOTE: 2. The drive control sets the high and low voltages to the gate of the Power FET driver (shunt switch). Both the upper and lower levels are set by values held in two of the sample/hold amplifiers. External capacitors at VUP1, 2 and VLOW1, 2 are required for stabilization. VLDX, VESDX ILDX 10A Peak Current 2 1 V A IRLY rDS(ON) 20 30 mA VREFR VTECG (To OT Output) TLOW THIGH VOL IOL VOH IOH 2.07 1.67 0 3.5 2.1 1.7 12 4 2.13 1.73 1.5 VCC - 0.5 V V V mA V mA 1.71 0 1.9 2.09 9 V V VOL IOL VOH IOH Programmed Current as Ref. 0 3.5 140 12 4 1.5 VCC - 0.5 % V mA V mA
4-6
HIP9022 Address, Timing and Waveforms
DIGITAL CONTROL S/H INT. TEST TEST NULL OR S/H
ADDRESS NUMBERS
#11 to 14
#1 to 8
#1 to 8
#1 to 8
#9 or 10 (NULL OR S/H)
#1 to 8
#15 (RESET)
SAMPLE (SH_B INPUT) NULLB INPUT VIN INPUT DIAGNOSTIC (DIAGINB INPUT)
FIGURE 2. ADDRESS WITH SAMPLE, NULL, VIN AND DIAGONAL WAVEFORMS TABLE 1. HIP9022 ADDRESS MAP A3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 NOTES: 3. The Idle address is protective in that SB_H input noise cannot disturb the chip if the Idle address is selected; also, the Address inputs are High (selecting Idle state) if the pins are open. 4. Address Numbers 9 - 11 are shaded to indicate test mode conditions and are shown for information only. These addresses are used in original production testing and not required for user applications. However, note that Address No. 15 will force a reset for Address Numbers 9 - 14. 5. Digital Programming: To set the digital addresses, only the proper digital address and a negative pulse >100ns on SB_H is needed. To reset the digital addresses to the default states, Address 15 and a SB_H pulse >100ns is needed. Normally the digital addresses will be set first, and the analog addresses programmed next. The test modes, Address Numbers 9 - 11, will normally only be used during factory testing. An address 15 Reset should normally precede most programming in order to assure that the digital address states begin in their default state. Otherwise, the digital address states will be undefined because there is no power-up-reset. 6. Analog Programming: To program the eight S/H circuits, addresses of 0-5V analog signal on VIN and negative pulses on NullB (10s) and SB_H (20s) pins are needed. The NullB pulse is valid only during the SB_H pulse and should occur during the first half of the SB_H pulse. The S/H amplifier is auto-zeroed for zero offset when both NullB and SB_H are low. The input VIN is captured on the S/H storage capacitor during SB_H low. 7. The Diagnostic mode reads map addresses 1 - 8 via the DIAG output when DIAGINB is low. A2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 ADDRESS NO. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FUNCTION TYPE ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG ANALOG DIGITAL DIGITAL DIGITAL DIGITAL DIGITAL DIGITAL DIGITAL DIGITAL FUNCTION NAME VIN(DL) Voltage for Constant Current Level, Laser Driver #1 VIN(DL) Voltage for Constant Current Level, Laser Driver #2 VLOWER Level, Laser Driver #1 VLOWER Level, Laser Driver #2 VUPPER Level, Laser Driver #1 VUPPER Level, Laser Driver #2 VIN(DL) Thermal Compensation Level, Laser Driver #1 VIN(DL) Thermal Compensation Level, Laser Driver #2 Test Mode: S/H Amp, Auto Zero Null Voltage (Note 4) Test Mode: S/H Amp Output Voltage (Note 4) Test Mode: Set VUP and VLOW Amps to Three-State (Note 4) VLOW#1 Set to Positive Output (Default is Negative) VLOW#2 Set to Positive Output (Default is Negative) Thermal Compensation Activated (Default is Deactivated) Reset Digital Address (9-14) to Default State Idle Condition (S/H Pin Defeated) (Note 3)
4-7
HIP9022 Circuit Block Descriptions
Laser Drive Circuitry
In Figure 3, the gate of the external current source Power FET, Q2 is driven via the Operational Transconductance Amplifier (OTA), A2 on the IC. The voltage on the current sense resistor, RS in the source of the Power FET is monitored by a X10 gain of the feedback amplifier, A1. The stability of the current loop is established with an external 0.1F capacitor to ground at the gate of the Power FET. The sampled voltage range is 0 to 0.5V when the proper value of sense resistor, RS is chosen (typically 0.25 for 2A). The OTA, A2 compares the X10 gain signal to a 0 to 5V reference signal from an on-chip Sample and Hold (First S/H) circuit. The Q2 drain current (Laser Drive current), IDL is:
V IN ( DL ) I DL = ------------------------( R S x 10 ) (EQ. 1)
A laser cools after it has been off for a period of time and is more efficient when it is turned-on. Compensation for the increased efficiency is made by slightly reducing the current level of the constant current source FET. The level will be reduced by a programmable amount of 0 to 5% of full scale. The programmable amount is fixed by the level of compensation to S/H addresses 7 and 8 (see Table 1). The percent of modulation (change) in drive current is calculated as follows:
V IN ( TC ) Modulation = --------------------- x 5 V IN ( DL ) (EQ. 2)
For example, if we control the Laser Drive current with 2V programmed with address 1 and 2 for the First S/H's, given that VIN(DL) = 2V and RS = 0.25. Then, from EQ. 1, IDL = VIN(DL)/(RS x 10) = 2/(0.25 x 10) = 0.8A. If 2V is programmed to addresses 7 and 8 as Thermal Compensation, VIN(TC) for the 4th S/H's, then, Mod.% = (2/2) x 5% = 5%. In Figure 3, the correction is applied from the output of the Thermal Compensation circuit (where the current is 2V/20k = 0.1mA) to the input of amplifier A2. The 0.1mA is forced into the 1k resistor (and the low Z output of A1) to increase the voltage at the inverting input of A2 by 0.1V or 5% of the +VIN(DL) input (2V) to A2. The modulation input is limited by the 0 to VCC input range of S/H maximum VIN.
where VIN(DL) is the programmed VIN for the First S/H voltage reference signal. The S/H reference for the Laser Drive Current current is updated with other multiplexed S/H circuits from a serial bus and an off-chip D/A converter. Laser constant current is fully controllable by the multiplex analog S/H bus, allowing accurate calibration of the laser output and corrections as the laser ages. In Figure 1, the laser drive current from Q2 is digitally switched to either flow through or is shunted around the laser diode by switching the external Shunt Power FET, Q3 on or off. The gate of the Shunt FET is switched between two voltages (Upper and Lower) which are provide by 2nd and 3rd S/H circuits. These Shunt FET gate drive levels are fully programmable via the multiplexed analog S/H bus. By adjusting these levels to account for the laser power supply, the Shunt FET threshold and channel resistance; minimum Shunt FET gate drive power levels can be established. The Upper and Lower gate voltage driver circuits are two high current OTA amplifiers with two filter capacitors. The upper voltage is programmable in the 0V to VCC range at the input of amplifier A4. The lower voltage is programmable in the range of -4V to VCC. The -4V extension is accomplished by an optional on-chip voltage inverter circuit. The input to amplifier A3 is either direct from the S/H input or inverted by amplifier A5. The maximum laser on-off switching speeds are dependent on the selection of Shunt FETs. A Harris dual complementary MOSFET, RF3V49092 or RF3S49092 has been designed specifically for this application. With the constant current set at 0.8A, a typical laser switching speed of 20ns has been measured.
Input Data
Q2 A2 +
1k
55 CC2 A1 + X10 54 XTEN2+ XTEN2OC2 49 0.1F RS 0.25
-
53
12k +
O. C. COMP.
30k
VOLT. TO CURRENT 27k 51 CTC2-27K 0.1F
THERMAL COMP.
+ 10k 52 CTC2-10K 0.02F
Thermal Compensation
A 4th S/H circuit is used to set the amplitude of an optional thermal compensation signal which can be used to modulate the constant laser current source as a two pole filtered effect of the laser on-off data. This feature may be disabled when it is not required. This circuit is designed to compensate for the temperature variations in the laser as the laser is turned on and off. The bypass capacitors at the Thermal Comparator (CTCx-10K, CTCx-27K) represent the respective poles for the filter.
VOLT. TO CURRENT 20k
S/H SYS FIGURE 3. LASER CONSTANT CURRENT SOURCE DRIVER WITH OVER CURRENT DETECTION AND THERMAL COMPENSATION
4-8
HIP9022
Both analog and digital data is input to control the action of the dual laser driver. Address codes and input data are described in the Table 1 Address Map. Digital data is normally entered first, followed by the analog data via the multiplexed analog bus which updates the S/H stored voltage levels. Four bit digital addresses to pins A3, A2, A1 and A0 are decoded to define the programming functions for data input. It is important to note that Address 15 is a reset for Addresses 9 - 14 and should be performed as the first step in programming because there is no power-onreset on-chip. resistor and drives the gate of the TEC FET driver. As such, the TEC circuit senses the thermo-resistor input as a measure of the laser temperature and the TEC drive is adjusted to maintain a stable Laser temperature slightly below the ambient temperature. An external Power FET is needed to provide the high TEC driver currents. An out of range temperature output for each laser is also provided.
Laser Protection Diodes
Another feature included on the chip is two high current ESD diodes which, in the printer system, are used to protect the Laser Diodes from ESD damage. Another component of Laser protection in printer systems are relays to disconnect the Lasers when in a non-operating mode. For this purpose, a single relay driver is included.
Diagnostic Output Data
For the purpose of monitoring on-chip signals, the multiplexed bus can be used to output signals (at the DIAG pin) via an analog diagnostic amplifier. This mode has the capability to monitor the multiplexed output of four (0-5V) analog signals for each laser channel. Note that the diagnostic information at the VLOW (Amplifier A3) output is 2:1 resistor divided to +5V (VCC) to return this signal to a 0 to 5V range. To minimize noise problems the monitoring function is normally performed during the laser scan for only one signal per scan. In addition, there are 3 test modes which allows the bus to present analog signals for testing the performance of the eight S/H circuits.
Over Current Flag Output (OC1, OC2)
Over-current detection is also included on-chip. The circuit of Figure 3 shows the over current detection circuit. For each laser source current driver, the over current monitor compares the S/H input of amplifier A2 to the output of amplifier A1. If the output voltage of A1 exceeds the input of A2 by 40%, then an over current state exists and the OC output will go high.
Invert Option
An INVERT input reconfigures the device such that the constant current source can be high side instead of the normal low side. This provides functionality for driving laser diodes in a common cathode configuration as opposed to the normal common anode configuration. The INVERT must be low (or open with the internal pull down) for the Figure 1 circuit.
Thermo-Electric-Cooler (TEC) Circuitry
Figure 4 shows the Thermal Electric Cooler (TEC) drive circuit with an external reference resistance, a thermoresistor to sense temperature plus feedback components for stable drive. There is a thermo-resistor reference input on the chip for monitoring the laser's temperature via a 5-10k thermo-resistor which must be mounted near the laser. A reference voltage on the external reference resistor is established by a current from a stable bias source. This current is mirrored to the thermo-resistor (one for each laser driver system). A comparator senses the voltage across the reference resistor versus the voltage across the thermo+ CURRENT MIRROR 1 1.9V + 2 + TECFB2
Reset Action
The RESETB (active low) controls three things: (1) The TEC driver is turned off. (2) The Shunt driver is turned on to turn off the laser. (3) The Constant current driver is turned off.
48
-
-
47 TECREF2 Q2
+
-
+
46
TECGDR2
LASER2 THERMORESISTOR (TEMPERATURE SENSOR)
45 O.T. TEMP. COMP. U.T. 43 44
TRES2 TEC OT2
TECREFR REFERENCE RESISTOR
THERMALLY COUPLED COMPONENTS
FIGURE 4. TEC (THERMAL ELECTRIC COOLER) CIRCUIT WITH REFERENCE RESISTOR AND THERMAL RESISTOR SENSOR OF LASER TEMPERATURE
4-9
HIP9022 Plastic Leaded Chip Carrier Packages (PLCC)
0.042 (1.07) 0.048 (1.22) PIN (1) IDENTIFIER C L 0.042 (1.07) 0.056 (1.42) 0.050 (1.27) TP
N68.95 (JEDEC MS-018AE ISSUE A)
0.004 (0.10) C
68 LEAD PLASTIC LEADED CHIP CARRIER PACKAGE INCHES SYMBOL A A1 MIN 0.165 0.090 0.985 0.950 0.441 0.985 0.950 0.441 68 MAX 0.180 0.120 0.995 0.958 0.469 0.995 0.958 0.469 MILLIMETERS MIN 4.20 2.29 25.02 24.13 11.21 25.02 24.13 11.21 68 MAX 4.57 3.04 25.27 24.33 11.91 25.27 24.33 11.91 NOTES 3 4, 5 3 4, 5 6 Rev. 2 11/97
0.025 (0.64) R 0.045 (1.14)
D2/E2 C L E1 E D2/E2 VIEW "A"
D D1 D2 E E1 E2 N
D1 D 0.020 (0.51) MAX 3 PLCS
A1 A
0.020 (0.51) MIN
SEATING -C- PLANE 0.026 (0.66) 0.032 (0.81) 0.013 (0.33) 0.021 (0.53)
0.045 (1.14) MIN
0.025 (0.64) MIN VIEW "A" TYP.
NOTES: 1. Controlling dimension: INCH. Converted millimeter dimensions are not necessarily exact. 2. Dimensions and tolerancing per ANSI Y14.5M-1982. 3. Dimensions D1 and E1 do not include mold protrusions. Allowable mold protrusion is 0.010 inch (0.25mm) per side. Dimensions D1 and E1 include mold mismatch and are measured at the extreme material condition at the body parting line. 4. To be measured at seating plane -C- contact point. 5. Centerline to be determined where center leads exit plastic body. 6. "N" is the number of terminal positions.
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Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
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Sales Office Headquarters
NORTH AMERICA Intersil Corporation P. O. Box 883, Mail Stop 53-204 Melbourne, FL 32902 TEL: (407) 724-7000 FAX: (407) 724-7240 EUROPE Intersil SA Mercure Center 100, Rue de la Fusee 1130 Brussels, Belgium TEL: (32) 2.724.2111 FAX: (32) 2.724.22.05 ASIA Intersil (Taiwan) Ltd. 7F-6, No. 101 Fu Hsing North Road Taipei, Taiwan Republic of China TEL: (886) 2 2716 9310 FAX: (886) 2 2715 3029
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